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The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time. 13.3 (1) Variables declared as global in an HLL can be assigned memory locations by the compiler, and all machine instructions that reference these variables will use memory-reference operands. (2) Incorporate a set of global registers in the processor. These registers would be fixed in number and available to all procedures 13.4 One instruction per cycle. Register-to-register operations. Simple addressing modes. Each D phase adds delay, so that term still must be included. Finally, each jump wastes the next instruction fetch opportunity. However, as can be seen in Figure 13.6, the data fetch is not completed prior to the execution of the following instruction. If this following instruction utilizes the fetched data as one of its operands, it must wait one phase. Solution Manual Computer Organization And Architecture 8th Edition.pdf. TABLE OF CONTENTS ITrtroduction.essescssessssesecsseeseeesneessneeeenee Computer Evolution and Performance. Operating System Support. Computer Arithmetic. Instruction Sets: Characteristics and Functions Instruction Sets: Addressing Modes and Format: Processor Structure and Function. Reduced Instruction Set Computers. Instruction-Level Parallelism and Superscalar Processor: Control Unit Operation. Microprogrammed Contro Parallel Processing. Multicore Computers. Number Systems Digital Logic. The instruction contains the address of the data we want to load. During the execute phase accesses memory to load the data value located at that address for a total of two trips to memory. 2.3 Toreada value from memory, the CPU puts the address of the value it wants into the MAR. The CPU then asserts the Read control line to memory and places the address on the address bus. Memory places the contents of the memory location passed on the data bus. This data is then transferred to the MBR. To write a value to memory, the CPU puts the address of the value it wants to write into the MAR. The CPU also places the data it wants to write into the MBR. The CPU then asserts the Write control line to memory and places the address on the address bus and the data on the data bus. When an address is presented to a memory 2.7 2.8 2.9 module, there is some time delay before the read or write operation can be performed. While this is happening, an address can be presented to the other module. For a series of requests for successive words, the maximum rate is doubled. The discrepancy can be explained by noting that other system components aside from clock speed make a big difference in overall system speed. A system is only as fast as its slowest link. In recent years, the bottlenecks have been the performance of memory modules and bus speed. As noted in the answer to Problem 2.7, even though the Intel machine may have a faster clock speed (2.4 GHz vs. 1.2 GHz), that does not necessarily mean the system will perform faster. Different systems are not comparable on clock speed. Other factors such as the system components (memory, buses, architecture) and the instruction sets must also be taken into account. A more accurate measure is to run both systems on a benchmark. Benchmark programs exist for certain tasks, such as running office applications, performing floating-point operations, graphics operations, and so on.