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analog ic design lab manualLaboratory Manual Lab 1 Cadence is a powerful design and simulation tool and it is crucial when it comes to analog and radio circuit design on chip. In this manual the long way through the menus will be shown every time something new will be done but the short command, if there is any, will also be shown. The short command will be shown in brackets next to the command, e.g. add instance (i). Also, notice that Cadence is case sensitive. Introduction As you have seen in the lectures the transistor has three regions of operation which is determined by the DC voltages V DS, V GS and V Th. How to extract the parameters is described in the next section. Parameter Extraction by Local Fitting Method The method of local fitting means that each of the mosfet parameters is measured in the working region of the transistor where it dominates. In this way, only a small number of simulations are necessary, which makes the method easy to perform. The main drawback is that it is very model dependent, i.e. a unique measuring program has to be designed for each model. Let us first have a look at the n-channel transistor in its linear region (small V DS ). In the model the drain current is modeled as in equation (2). It is advisable to set a small value for V DS to achieve a wide linear range of operation. Figure 1: Extraction of the threshold voltage. See Eq and in the textbook. The drain current, in this region, is described by equation (3). See figure 2. Figure 2: Measuring the channel length modulation factor.Why is the current mirror used? 5. Calculate the reference current (I ref ) and width (W) of the transistors in a 1:1 PMOS current mirror. Introduction to Cadence and simulation of a mosfet:s DC parameters Start a terminal window and create a folder for the laboratory sessions. Open the folder and initiate Cadence with the command inittde ana20xx. Cadence uses many windows and it is not unusual to have six windows opened at the same time.http://ecohost.ru/pics/images/kenwood-ts-440-manual-pdf.xml
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To make it a bit easier and to get a good overview one suggestion is to use more than one desktop. It also logs all the commands and activities you perform, you can always check here if something isn t working. Library Manager, see figure 4, shows the different libraries with its content. You will now create your own library that will be used during the laboratory sessions of this course. Write a name for your library, e.g. analogic, and click OK. In the next window you choose Attach to an existing techfile and click OK. In the The library will now appear in the library list in Library Manager. Figure 4. Library manager You should now create you first cell or circuit in Cadence. See figure 5. Click OK. Your cell will now be created and a Schematic Editing window will open. It is in this window that you will design your circuit. Figure 5. Create schematic. Let s create a simple schematic like the one in figure 6. This circuit can be used to test the DC operation of a single MOSFET and compare it to the homework assignment. This part of the lab is also intended to get you familiar with Cadence schematic.Add Instance In the new window appearing, Add Instance, click on Browse.Another important library is analoglib. Here you find fundamental circuit elements such as ground and vcc symbols, voltage and current sources, resistors, capasitors, etc. The circuit elements in this library are ideal and have no parasitics, mismatch or other non-idealities. If the window Library Browser Add Instance is still opened just click on analoglib in the Library menu and find the following elements: vdc and gnd. Hint: you can write the name of the cell in the box under the headline Cell to find your element faster e.i. you don t have to scroll down. If you already closed the Library Browser Add Instance window just add an instance as described earlier (i). Add the elements to your schematic according to figure 6.http://buyanycarnow.com/uploadedfiles/kenwood-ts-440s-manual.xml When you re done adding your circuit elements just press the escape button on the keyboard to close the add instance windows. Escape is one of your best friends in Cadence as it cancels the command you re currently using, e.g. adding instances, wires or moving objects. Make it a habit to press it when you are done with your latest command and get used to press the Esc button a lot. Add Wire (narrow) Connect the elements by left clicking on the red contacts. You can also click anywhere in your schematic window to fasten the wire there before continue to the next contact. In the Edit menu you will also find useful commands as: undo (u), redo (U), stretch (m), copy (c), delete (Delete) and rotate (right mouse click). The difference between move and stretch is that with stretch the wires connected to the element will follow as you move the element and the connection will not be broken but with move the element will be moved out of the circuit. The schematic should looking like the one in figure 7. You should now edit the properties of the NMOS. A new window opens called Edit Object Properties. Take a look of the different properties that can be changed. Edit the Width and Number of fingers according to figure 8. Wire (narrow) (w) or use the icon on the left toolbar.When you are designing and simulating a circuit you often want to try different widths of a transistor or different bias voltages to find an optimal design. To make this easier you can use Design Variables in your schematic. Edit the property DC voltage of the two DC voltage sources and write Vgate and Vdrain respectively as their DC voltage, see figure 9. Your schematic is ready for simulations and should be saved. Press on the button Check and save in the left menu. Every time you change something in your schematic you have to press Check and save before you run your next simulation. Most of the time when a simulation won t start, you have forgot to press Check and save.http://www.raumboerse-luzern.ch/mieten/boss-gt-8-manual-espa-ol-pdf Check and save To start the simulation tool Analog Environment go to the Tools menu at the top of the schematic window and then choose Analog Environment. A new window will appear called Virtuoso Analog Environment. WaveScan and AWD is two different plot tools and most of the differences are in the appearances e.i. they can perform the same operations. Which one you choose is mostly up to you but now we need to save some data to a text file and then AWD the one to use. The new pop up window contains all different simulations that can be performed and now we will do a dc simulation. The variable names will now appear in the lower left corner under the headline Design Variables in the Analog Design Environment window. To edit the value double click on the variable name and type the value of the variable in the box, do not forget to click on the Change button to save the change. Set Vgate to 900m (this represent 900mV) and Vdrain to 50m.Analog Environment with design variables set and a dc analisys ready to go. Now you are ready to run the simulation. A new window will appear, Results Display Window, with a list of variables from the mos-transistor. You can find the value of e.g. the gate-to-source capacitance cgs, the channel resistance ron int the linear region, the threshold voltage vth and the drain-to-source current ids. A new window appears, write Vgate at the Variable Name and sweep from 0 to 1.2. Use 25 steps with automatic step control. See figure 12. This will overwrite the value you have given Vgate in the Analog Environment window and sweep it from volt while Vdrain will remain unchanged.You will now look at another important tool, the calculator. It can perform a lot of operations and can plot the result. Now click on the op button, stands for operation point, and a new window named Select an instance will appear. Click on the nmos in the schematic, the name of the window will now change to something like OP parameters for M0, see figure 13.http://www.gelbyson.com/images/96-cutlass-supreme-manual.pdf Select ids in the list and click OK, a line of text will appear in the calculator indicating the ids current of the nmos you selected, see figure 14. Back to the calculator and press the printvs button. Just click OK in the next window and the simulated values used to plot the graph will be presented in a list, in a new window called Results Display Window. Choose Print To File and write a good File Name and end with.txt. See figure 13 for an example. The file will be saved in the directory where you initiated and ran Cadence. Use this data in Matlab to plot the curve and extract the threshold voltage and ( ) according to this manual and the homework assignment. Compare your k with the one from the datasheet. You do not have to do it now but the plot and extraction should be included in the lab rapport. Note the threshold voltage from Cadence operating point as before to compare it with your extracted value later. Figure 13. To the left, OP parameters. To the right, printvs window. Calculator menu in Analog Environment, the calculator will open.HINT: If you want to make a picture of a schematic in Cadence you don t have to print screen and get the black background instead you can use a plotting tool from Cadence. A new windows opens, Submit Plot, and in the lower right corner there is a button called Plot Options, click it for another window with the same name to open. Here you should choose Plotter Name to be EPS and don t forget to change Scale to 1 (or some other value that makes a reasonable large picture). Choose Send Plot Only To File and write the full file path. When you are in the desired directory in your Unix terminal window just write pwd to get the path to that directory. Now just copy that path and add filename.eps. Click OK in both Plot Options and Submit Plot. The schematic will be saved as an EPS picture in black and white and can be used for reports and presentations. See figure 15 and 16.The cellview is a box representation of the current mirror schematic, which will be used to simulate the DC output resistance of the current mirror using a testbench. Add Instance Give the transistors the width and length from homework assignment 5; divide the transistors into 2 fingers. The Vdd terminal is found in analoglib and cellview name is vdd. The complete current mirror should look like figure 18. Symbol Generation Options Window Save the symbol and close the symbol window and the Schematic window. Now a symbolic view of the current mirror is created. This means that the current mirror can be instanced like any of the other components. Library: analogic, Cellview: CurrentMirror and View:Symbol. The additional instances (Vdd, gnd, Idc and Vdc ) are found in analoglib. Start by building the power supply, see figure 20. Set the DC voltage of the DC source to 1.2V. Figure 20. Schematic of the power supply Connect the DC current source (idc) between gnd and the In pin of the current mirror cellview.Connect a DC voltage source (vdc) between gnd and the Out pin, name the DC voltage of the source to Vds (In order to get the signs right). The test bench should look like figure 21. When done Check and Save Figure 21. Sweep from -1.2 to -0.1 with a linear step size of 0.1, the form should look like figure 22. Instance (i), click on the Browse button. Plot the output current of the current mirror use the idc function in the calculator. In addition save the current as a text file as well. In order to calculate the output resistance you must first derive the drain source current (Ids) as a function of the drain source voltage (Vds). To derive the drain source current, use the derive function under special functions. Press the Add button to add a new subwindow, click OK and plot the new result (also print the result to a text file). The derived result is the channel conductance which is the inverse of resistance, so use the calculator to invert the result and plot this result in a new subwindow as well (also print this result to a text file). Compare your results with the home work and discuss your findings. Figure 24. Functions need in the calculator to plot the output resistance of the current mirror 22 Layout of a PMOS current mirror in Cadence In the final part of the lab you will finalize a layout of the same Current Mirror you simulated in the previous section. Start by clicking on the Library called LayoutLab1, right click on the layout view of the CurrentMirror cellview, and choose copy. Change the To Library to analogic (see figure 25), click OK and in the next window that appears click on the Fix Error button and after that click OK. Figure 25. The Copy View form 23 Open the layout view of the CurrentMirror cellview, the layout is shown in figure 26. To zoom in you just have to press z on the keyboard and click and drag over the area which you want to zoom into. The Layer Select Window (LSW) 24 We start by looking at the LSW, displayed in figure 27. The LSW is used to select each layer in the process stack i.e. the different layers provided by the foundry; the layers are both metal and different layers to build the actual semiconductors. Start by marking the Diff layer in the LSW, then click on the NV icon button in the LSW. By pressing the NV only the Diff layer is highlighted, now return to the layout window. First press f on the keyboard and now you see that only the Diff layer is visible. To get all layers visible again, push the AV button in the LSW. Now go back to the layout window and press f on the keyboard. This works for all the layers in the stack. Next is to learn how the ruler works, the ruler is the most used tool during layout. Now we should measure the width and length of the big rectangle in metal layer 2 (ME2). Start by pressing k on the keyboard; click the pointer in one of the corners of the rectangle now you should just drag the pointer the corner on opposite side of the rectangle. Use the ruler to measure both the length and width of the rectangle. Choose 7 Rows in the create contact form (figure 28) and place the contact on the edges of the poly-silicon as displayed in figure 29. Finally choose 3 Columns and place the contact as centered as possible on the upper left source region. Now copy(c) the contacts to all the other source metals. Finally choose 12 Columns and place the contact above the 2 transistors and another one underneath. Now select NWEL in the LSW and draw a rectangle around both the transistors and the nwell contacts. Save the layout! Figure 31. Placement of the bulk contacts and NWell Now we have done some changes to the layout, then it is time to run the Design Rule Check (DRC). The DRC does just what it says; it checks if all the rules for the process are fulfilled i.e. these rules are of different variety, for examples if two metal wires are to close or if the wires are too narrow. Click Apply, when the DRC has completed a display window emerges. If there are some errors click and highlight them. Fix the errors and if there are no errors continue. Do not forget to save the layout. Now run an additional DRC with the Rule Set menu at 1P8M2T20kA-BOEL (Checks the Metal Stack). Do not forget to save the layout! 27 Figure 32. DRC Setup Form Now it is time to connect all the individual terminals together. First we will connect the gates together. Start by selecting ME1 in the LSW, now we will add a metal1 path between the metal1 to poly contacts. Now connect the drain of the left transistor to the gates by using the path (p) in metal 1 (ME1). The left transistor should look something like figure 33. Figure 33. The Diode-Connected Transistor 28 Now select metal2 in the LSW and draw a path from the bottom nwell contact (over the left transistor) up to the metal 2 rectangle. Draw an additional path over the right transistor, your layout should look something like figure 34. Adjust the width of the paths so they can handle a current of 1.2mA (use the data sheet of the process) by selecting the path and pressing q on the keyboard. Figure 34. Sources and bulks connected to the VDD plane Figure 35. Draw a path of equal length from the drain of the right transistor, after this step the layout should look something like figure 35. Save your layout and run both DRC:s. 29 Now we should define all nodes in the layout, by place labels. The final layout should look something like figure 37. Correct any errors and continue. Figure 37. Final Layout 30 When the layout of the design is DRC clean we should continue with an additional check which is too verify that the layout and the schematic of the current mirror are the same. Click Apply. When the LVS has completed a display window emerges, if there are some errors scroll down the log and try to solve the errors. Check if all contacts are present and verify that there are no short circuits in your layout. Figure 38. LVS Setup Form Laboratory Report Compose a report containing the difference of calculated and simulated values. The report should also answer the questions in the homework section, and explain the results from the laboratory. Include plots of the simulated figures. You will use the MOSFET as a variable resistor and as a switch.The software All rights reserved. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify However, within your own VI you will use LabVIEW supplied This Ribbon system replaces the traditional menus used with Excel 2003. Above the Ribbon in the upper-left corner is the Microsoft Starting Statgraphics 1. Log in to your PC, using the usual procedure It also serves as an introduction to the data analysis capabilities Windows XP Getting Started on the Computer With Mouseaerobics. Windows XP Send any corrections and comments Keywords Printed Circuit Logic Gate A logic gate is an elemantary building block And there are several popular commercial packages. The small-signal drain current due to v gs is therefore given by The examples shown here would be for NMOS. Figure After you have completed the tutorial, you should be able to begin creating your Dynamic Mathematics Software in one easy-to-use package For learning and teaching at all levels of education Joins interactive 2D and 3D geometry, algebra, October 6, 2005 The student will apply circuit analysis techniques WELCOME TO WINDOWS 7 After you log into your machine, the Page 1 1997 2001 DASSAULT SYSTEMES.Message To show how CATIA V5 allows the user to automatically generate associative drafting Various parts of the display are labelled in red, with arrows, to define the terms used in the remainder of this overview. MOSFET Current Mirrors. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and Bob Booth July 2008 AP-PPT5 Bob Booth July 2008 AP-PPT5 University of Sheffield Contents 1. INTRODUCTION. 3 2. GETTING STARTED. 4 2.1 STARTING POWERPOINT. 4 3. THE USER INTERFACE. Step 1: Locate the Touchpad. The Touchpad is used to navigate the cursor Examples would be File and Analysis. ALL The most common datum features include planes, axes, coordinate systems, and curves. Datum features do March 6, 2003 You can click on a shortcut on your desktop Come learn the computer basics at the Muhlenberg Community Library. This The tutorials that follow continue with the same plan. When we are finished, we will have created Add text to your poster 14. Add pictures to your poster 17. Add graphs Set up the spreadsheet page (Sheet 1) so that anyone who reads it will understand the page (Figure 1). Type With QuickBooks Layout Excel is powerful tool and can make your life easier if you are proficient in using it. You will need to use Excel to complete most of your Introduction To Mentor Graphics Mentor Graphics BOLD browser allows Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design Then in PowerPoint: (A) set up the poster size and orientation, (B) add and Each student is responsible for learning Purpose The purpose of this lab is to examine the properties Consider the circuit shown in The following are the outlines: 1. Start Microsoft Word 11.Behind the scenes, Capture generates a netlist It combines a full featured integrated development environment (IDE) with a powerful visual programming interface. The two tools Open existing Templates Create Working With Objects Nontext elements in a document are referred to as Objects Excel 2013 Level 1 A self-biased n-channel JFET with an AC Why Use LTspice? Stable SPICE circuit You can use Access to manage anything from a home inventory to a giant To use this website, you must agree to our Privacy Policy, including cookie policy. To browse Academia.edu and the wider internet faster and more securely, please take a few seconds to upgrade your browser. You can download the paper by clicking the button above. Related Papers TUTORIAL CADENCE DESIGN ENVIRONMENT By Shilpa Joseph Electric Manual-9 03 By Awad Sayed Space user’s manual By Nick van der Meijs and A. Van Genderen A novel VLSI layout fabric for deep sub-micron applications By Alberto Sangiovanni Vincentelli Fast computation of substrate resistances in large circuits By Nick van der Meijs READ PAPER Download pdf. The following topics are covered in the class: MOSFET modeling for analog circuit design Single-stage Amplifiers Differential Amplifiers Active and Passive Current Mirrors Frequency Response Noise Feedback Operation Amplifiers Stability and Frequency Compensation Bandgap References Switched Capacitor Circuits Nonlinearity Mismatch in Analog Circuits The textbook for this class is the Design of Analog CMOS Integrated Circuits by Behzad Razavi. For access to the labs please contact John Kazana at kazana at ee dot columbia dot edu To obtain a username and password, please contact Quy at qgo1 at columbia dot edu. Use virtuoso (cadence v6) and not icfb (cadence v5) for all homeworks and projects. Discover everything Scribd has to offer, including books and audiobooks from major publishers. Start Free Trial Cancel anytime.Browse Books Site Directory Site Language: English Change Language English Change Language Quick navigation Home Books Audiobooks Documents, active. First, the basic devices of CMOS circuit design, the NMOS and PMOS transistors, are introduced and analog design environment lab manual characterized. Analog Environment, and analog design environment lab manual the Cadence Analog Design Environment window will open. Alternatively, you can analog design environment lab manual launch this tool from the CIW by selecting Tools Analog Environment Simulation in the CIW. Attend all the lab sessions without fail. You will apply theorem to analyze an R-2R ladder network. Analog and Digital munication Lab Manual Pdf at. Analog Lab Arturia. Discovery Virtuoso Analog Design Environment L Cadence. It is focused on the design of low-power and low-voltage analog and RF CMOS integrated circuits, on the modeling of advanced semiconductor devices with a particular focus on the MOS transistor for analog and RF design, and on the design of low-power error tolerant circuits and systems. The strong background acquired over the years in compact modeling of the MOS transistor with the EKV model and its related design methodology applied to analog and RF circuits, helps finding optimum circuit solutions. Radhika Nagpal Negar Kiyavash. Amir Zamir Ramon Llull and the ars combinatoria Les Outrenoirs de Pierre Soulages. Please help to improve this article by introducing more precise citations. ( March 2019 ) ( Learn how and when to remove this template message ) The metal layer is coloured blue, green and brown are N- and P-doped Si, the polysilicon is red and vias are crosses. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography.Digital IC design is to produce components such as microprocessors, FPGAs, memories ( RAM, ROM, and flash ) and digital ASICs. Digital design focuses on logical correctness, maximizing circuit density, and placing circuits so that clock and timing signals are routed efficiently. Analog IC design also has specializations in power IC design and RF IC design. Analog IC design is used in the design of op-amps, linear regulators, phase locked loops, oscillators and active filters. Analog design is more concerned with the physics of the semiconductor devices such as gain, matching, power dissipation, and resistance. Fidelity of analog signal amplification and filtering is usually critical and as a result, analog ICs use larger area active devices than digital designs and are usually less dense in circuitry.An average desktop computer chip, as of 2015, has over 1 billion transistors. The rules for what can and cannot be manufactured are also extremely complex. Common IC processes of 2015 have more than 500 rules. Furthermore, since the manufacturing process itself is not completely predictable, designers must account for its statistical nature. The complexity of modern IC design, as well as market pressure to produce designs rapidly, has led to the extensive use of automated design tools in the IC design process. In short, the design of an IC using EDA software is the design, test, and verification of the instructions that the IC is to carry out. An integrated circuit some times called chip or micro chip is a semi conductor which thousands of millions of tiny resistors, capacitors, and transistors are fabricated. An IC can function as an amplifier, oscillator, timer, counter, computer memory or micro processor.A method to isolate the individual components formed in the substrate is necessary since the substrate silicon is conductive and often forms an active region of the individual components. The two common methods are p-n junction isolation and dielectric isolation. Attention must be given to power dissipation of transistors and interconnect resistances and current density of the interconnect, contacts and vias since ICs contain very tiny devices compared to discrete components, where such concerns are less of an issue. Electromigration in metallic interconnect and ESD damage to the tiny components are also of concern. Finally, the physical layout of certain circuit subblocks is typically critical, in order to achieve the desired speed of operation, to segregate noisy portions of an IC from quiet portions, to balance the effects of heat generation across the IC, or to facilitate the placement of connections to circuitry outside the IC.The user may use a variety of languages and tools to create this description.The RTL describes the exact behavior of the digital circuits on the chip, as well as the interconnections to inputs and outputs. This involves figuring out which gates to use, defining places for them, and wiring them together. The third step, physical design, does not affect the functionality at all (if done correctly) but determines how fast the chip operates and how much it costs.The various phases of the integrated circuit development process are described below. Although the phases are presented here in a straightforward fashion, in reality there is iteration and these steps may occur multiple times.The requirements are usually generated by a cross functional team that addresses market opportunity, customer needs, feasibility and much more. This phase should result in a product requirements document.It defines high level concepts and the intrinsic value proposition of the product. Architecture teams take into account many variables and interface with many groups. People creating the architecture generally have a significant amount of experience dealing with systems in the area for which the architecture is being created. The work product of the architecture phase is an architectural specification.It implements the architecture and defines specific mechanisms and structures for achieving that implementation. The result of the micro-architecture phase is a micro-architecture specification which describes the methods used to implement the architecture.This involves low level definition and partitioning, writing code, entering schematics and verification. This phase ends with a design reaching tapeout.Bringup is the process of powering, testing and characterizing the design in the lab. Numerous tests are performed starting from very simple tests such as ensuring that the device will power on to much more complicated tests which try to stress the part in various ways. The result of the bringup phase is documentation of characterization data (how well the part performs to spec) and errata (unexpected behavior).Although a design may have successfully met the specifications of the product in the lab during the bringup phase there are many challenges that product engineers face when trying to mass-produce those designs. The IC must be ramped up to production volumes with an acceptable yield.