i.mx25 multimedia applications processor reference manual
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i.mx25 multimedia applications processor reference manualRelevant discussion may be found on the talk page. Please do not remove this message until conditions to do so are met. ( October 2018 ) ( Learn how and when to remove this template message ) The series was later renamed to i.MX. It was launched in 2003.It was launched in 2007.It especially integrates key security features in hardware.This unique integration removes the need for external power management chip and audio codec chip.It especially integrates key security features in hardware, an ADC and the power management unit. It supports mDDR, LV-DDR2, DDR2-SDRAM at 200 MHz.It supports mDDR-SDRAM at 133 MHz. The 3D and VPU acceleration is provided by the PowerVR MBX Lite.It was launched in 2008.It supports DDR2-SDRAM at 133 MHz.It comprises two families: the i.MX51 family (high-end multimedia devices like smartbook or automotive infotainment) and the i.MX50 family ( eReaders ). It is designed in CMOS 65 nm process.The imx51 family was launched in 2009.It is dedicated for eReaders. Launched in 2010, it integrates the E Ink display controller within the silicon to save both BOM cost and space on the PCB. It especially supports LP-DDR2 SDRAM at 400 MHz.Shipped since the first quarter of 2011.It is designed in CMOS 40 nm process.Within each series some versions are pin compatible.In previous CPU series the naming convention clearly corresponds to a function or feature set, but this is not the case with i.MX 8.The CPU was suggested to include varying counts of Cortex-A72, Cortex-A53 and Cortex-M4, while the GPU is either 1 or 2 units of the Vivante GC7000VX. All versions includes one or two Cortex-A72 CPU cores and all versions includes two Cortex-M4F CPU cores.The QuadPlus is using GC7000Lite cores, while the 'QuadMax' includes two full GC7000 GPUs.An extensive selection of high-speed interfaces enabling broader system connectivity, and targeting industrial level qualification, the i.http://dragoniresorts.com/userfiles/copystar-cs-1820-manual.xml
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MX 8M Mini family may be used in any general embedded consumer and industrial application.You can help by adding to it. ( August 2020 ) It is slated for 1 GHz performance on the Cortex-M7, and provides an additional Cortex-M4 co-processor.The last Ubuntu version supported is 10.04.1 (still available on mirrors).These include:Retrieved 2016-02-23. CS1 maint: archived copy as title ( link ) CS1 maint: archived copy as title ( link ) By using this site, you agree to the Terms of Use and Privacy Policy. The device is suitable Package Information Plastic package Case x 17 mm, 0.8 mm Pitch Ordering Information See Table 1 on page 3 for ordering information. The i.MX25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets. The device is suitable for a wide range of applications, including the following: Graphical remote controls Human machine interface (HMI) Residential and commercial control panels Residential gateway (smart metering) Handheld scanners and printers Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh. Interface flexibility--The device interface supports connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND. Increased security--Because the need for advanced security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads. On-chip PHY--The device includes an HS USB OTG PHY and FS USB HOST PHY.http://foryoursalon.com/userfiles/dragon-warrior-7-manual.xml Fast Ethernet--For rapid external communication, a fast Ethernet controller (FEC) is included. This multi- stage struc?ture is rated All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08DZ128 Series Low Power Fully Static Versions 80C186 80C188 Operation Modes Enhanced Mode DRAM Refresh Control Unit Power-Save Mode Direct Interface 80C187 (80C186XL Only) Compatible Mode NMOS 80186 80188 Pin-for-Pin Replacement for Non-Numerics Applications Integrated Feature Set Static Modular CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt. All rights reserved.The ARM946E-S, which is based on the five stage pipeline ARM9E-STM Har vard architecture processor, also contains. To receive product literature, visit us at LSI Logic Corporation reserves the right to make. Low Power Integrated X86 Solution. Serving the needs of consumers and business professionals alike, it is the perfect solution. Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory. Notice: This is not a final. Some parametric limits are subject to change. The 7542 Group is the 8-bit microcomputer based on the 740 family core technology. Basic machine-language. MPC500 Family Memory Map. The support of EDO DRAM memory type was de-emphasized since this edition. - Pin designation PWRONC was changed to RESET. No EDO DRAM and 64-bit DIMM support. Built-in. The instructions of the VR5000 and VR5000A are compatible with those of the VR3000TM Series and VR4000TM Series and higher, and completely compatible with those of the VR10000TM. Therefore, present applications can be used as they are.https://www.becompta.be/emploi/bosch-maxx-2260-manual Detailed function s are provided. The implementation is based on the European Space Agency (ESA) LEON2 fault tolerant model. By executing powerful instructions in a single clock cycle, the AT697 achieves throughputs approaching 1MIPS. Discover everything Scribd has to offer, including books and audiobooks from major publishers. Report this Document Download Now Save Save IMX25RM.pdf For Later 0 ratings 0 found this document useful (0 votes) 0 views 2,622 pages IMX25RM.pdf Uploaded by Dav Description: Full description Save Save IMX25RM.pdf For Later 0 0 found this document useful, Mark this document as useful 0 0 found this document not useful, Mark this document as not useful Embed Share Print Download Now Jump to Page You are on page 1 of 2622 Search inside document Browse Books Site Directory Site Language: English Change Language English Change Language. This tool uses JavaScript and much of it will not work correctly without it enabled. Please turn JavaScript back on and reload this page. More questions in i.MX Processors Where is this place located. NXP Community All Places i.MX Processors Log in to create and rate content, and to follow, bookmark, and share content with other members. Resets part of the data circuit and the DMA circuit. Resets part of the command circuit. Is RSTA reset equivalent to RSDT plus RSTC reset. The RSTC resets command agent, the RSTD resets data agent, the RSTA resets all controller. Please look at Figure 23-2 (enhanced Secure Digital Host Controller (eSDHC) Block Diagram) of the i.MX25 Reference Manual. Reset all internal buffers of eSDHC? (IP bus IF, internal Dual-Port Buffer RAM) What about eSDHC clocks and eSDHC interrupt registers. The RSTA should be used for the ENGcm07207. Regards, Yuri. Actions Related Content Retrieving data. Recommended Content eIQ Transfer Learning Lab with TensorFlow Lite for i.MX RT. Edit Place Overview Page Choose a layout and drag widgets onto your Overview Page to customize it.http://jms-servisni.com/images/bushnell-banner-astro-400-instruction-manual.pdf Widgets placed on the page below can be configured by selecting the symbol. OK Don't show me this again. i.MX Community NXP Community All Places i.MX Community More Overview Content People Images Subspaces Calendar More Actions About Share Log in to follow, share, and participate in this community. More Feeds Loading. Here you can find technical information and learn from your peers and from the NXP product experts to answer your questions about your i.MX and PMIC de sign. We would like to encourage you to please refer to the i.MX Home Page or Software and Tools Page to see if you might find an answer to your question. Also, please us e the widget below to first search the community and if you don't get an answer to your question, then submit a question. You might find someone has already solved your particular problem. For the description of the low-level SPI driver of the latest L4.1.15 BSP by NXP, please refer to the Chapter 36 of the attached document. Hello, I bought a IMX.6QP SABRE module just a few days ago and there is no SD card to boot it inside of the pack which is the delivered. I have some questions about the procedure i have done. I am using IMX.6QuadPlus SABRE board for Automotive Infotaintment and there was no sd card inside of the package for the first booting when it was delivered to me. So i am trying to boot it from Windows PC. Thanks Raj Like Show 0 Likes (0) Actions Takashi Takahashi in i.MX Community 1 day ago ( Show more Show less ) Chenge to USB PHY Receiver Control Register Hi community. Our customer has question below. Is it some of i.MX6 series family? If so, please specify what exacly i.MX6 processor (Quad, Dual, DualLite, Solo, SoloLite, SoloX, UltraLite) do you use.Automotive As drivers adopt personal and home-based smart devices, automotive manufacturers are bringing a similar experience in-vehicle. Able to meet demands of connectivity, real time data delivery, digital instrumentation, audio and multi-stream video, i.https://c2mag.com/wp-content/plugins/formcraft/file-upload/server/content/files/16297c2ecb348d---Computer-service-manual.pdfMX 6 series enables auto infotainment and instrument cluster designers to re-create today’s consumer technology experience in the car. Smart Devices The market for intelligent, multimedia centric, touch based devices is increasing exponentially.How satisfied are you with the community as a resource for technical information. Please respond to this poll to give us your opinion about technical information available in this community. Austin, TX This application note shows the interface between the i. MX25 processor and the mDDR and DDR2 memories. Also, this application note defines the routing guidelines for these two memories, with pictures and examples. 1 i. MX25 SDRAM Controller The SDRAM controller can interface with either SDR-SDRAM, Mobile DDR, or DDR2 -SDRAM memories. All rights reserved.Thank you, for helping us keep this platform clean. The editors will have a look at it as soon as possible. We've been trying to use. The reason why this In Chapter 43.1.2.1 Normal Mode, Page 43-5, it's explained that this No data is transferred Therefore, the SSI on the i.MX25 in Slave Mode (I don't know the other This kind of explaines also, why all multi channel examples from The only codec used in their PDKs on the. SSI is a plain stereo chip. To overcome this limitation, we've split up our working group and will BR Sven. Am 27.08.2010 13:45, schrieb Sascha Hauer. However, as soon as. Alsa-devel mailing list. In big endian, the order of the bytes is reversed EPIT Enhanced Periodic Interrupt Timer-a 32-bit set and forget timer capable of providing precise interrupts at regular intervals with minimal processor intervention FCS Frame Checker Sequence FIFO First In First Out FIPS Federal Information Processing Standards-United States Government technical standards published by the National Institute of Standards and Technology (NIST).alisawedding.com/upload/users/files/canon-vb-c300-manual.pdf NIST develops FIPS when there are compelling Federal government requirements such as for security and interoperability but no acceptable industry standards FIPS-140 Security requirements for cryptographic modules-Federal Information Processing Standard 140-2(FIPS 140-2) is a standard that describes US Federal government requirements that IT products should meet for Sensitive, but Unclassified (SBU) use Flash A non-volatile storage device similar to EEPROM, where erasing can be done only in blocks or the entire chip. Flash path Path within ROM bootstrap pointing to an executable Flash application Flush Procedure to reach cache coherency. Refers to removing a data line from cache. This process includes cleaning the line, invalidating its VBR and resetting the tag valid indicator. A hash value (or simply hash), also called a message digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and is generated by a formula in such a way that it is extremely unlikely that some other text produces the same hash value.NAND flash devices offer storage space up to 512-Mbyte and offers faster erase, write, and read capabilities over NOR architecture NOR Flash See NAND Flash PCMCIA Personal Computer Memory Card International Association-a multicompany organization that has developed a standard for small, credit card-sized devices, called PC Cards. There are three types of PCMCIA cards that have the same rectangular size (85.https://www.helpfulhunks.com.au/wp-content/plugins/formcraft/file-upload/server/content/files/16297c2efda924---computer-service-manual-pdf.pdf6 by 54 millimeters), but different widths physical address The address by which the memory in the system is physically accessed PLL Phase Locked Loop-an electronic circuit controlling an oscillator so that it maintains a constant phase angle (a lock) on the frequency of an input, or reference, signal RAM Random Access Memory RAM path Path within ROM bootstrap leading to the downloading and the execution of a RAM application RGB The RGB color model is based on the additive model in which Red, Green, and Blue light are combined to create other colors. The abbreviation RGB comes from the three primary colors in additive light models RGBA RGBA color space stands for Red Green Blue Alpha. The alpha channel is the transparency channel, and is unique to this color space. RGBA, like RGB, is an additive color space, so the more of a color placed, the lighter the picture gets. PNG is the best known image format that uses the RGBA color space RNGA Random Number Generator Accelerator-a security hardware module that produces 32-bit pseudo random numbers as part of the security module ROM Read Only Memory ROM bootstrap Internal boot code encompassing the main boot flow as well as exception vectors Table continues on the next page.USB also supports Plug-and-Play installation and hot plugging USBOTG USB On The Go-an extension of the USB 2.0 specification for connecting peripheral devices to each other.It does not contain all of the product-specific drivers, hardware-independent software stacks, Graphical User Interface (GUI) components, Java Virtual Machine (JVM), and applications required for a product.Linux OS facilitates timer use through various functions for timing delays, measurement, events, alarms, high-resolution timer features, and so on.The SPBA implementation under MSL defines the API to allow different masters to take or release ownership of a shared peripheral. SDMA API The Smart Direct Memory Access (SDMA) API driver controls the SDMA hardware.http://thanhlamresort.vn/wp-content/plugins/formcraft/file-upload/server/content/files/16297c2fb94448---Computer-system-a-programmer-s-perspective-2nd-edition-solution-manual.pdf It provides an API to other drivers for transferring data between MCU, DSP and peripherals. This API is standard Linux DMA engine API. SDMA is Linux DMA engine driver.. The SDMA controller is responsible for transferring data between the MCU memory space, peripherals, and the DSP memory space. The SDMA API allows other drivers to initialize the scripts, pass parameters and control their execution. SDMA is based on a microRISC engine that runs channel-specific scripts. Smart Direct Memory Access (SDMA) API All DMAC Both AHB-to-APBH and AHB-to-APBX DMA support configurable DMA descript chain. AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) All Low-level PM Drivers The low-level power management driver is responsible for implementing hardware-specific operations to meet power requirements and also to conserve power on the development platforms. Driver implementations are often different for different platforms. It is used by the DPM layer. Low-level Power Management (PM) Driver All CPU Frequency Scaling The CPU frequency scaling device driver allows the clock speed of the CPUs to be changed on the fly. CPU Frequency Scaling (CPUFREQ) Driver All Dynamic Bus Frequency Driver In order to improve power consumption, the Bus Frequency driver dynamically manages the various system frequencies. Electrophoretic Display Controller (EPDC) Frame Buffer i.MX 6DualLite, i.MX 6Solo, i.MX 6SoloLite, i.MX 7Dual PxP The Pixel Pipeline (PxP) DMA-ENGINE driver provides a unique API, which are implemented as a DMA engine client that smooths over the details of different hardware offload engine implementations. PXP DMA-ENGINE Driver i.MX 6DualLite, i.MX 6Solo, i.MX 6SoloLite, i.MX 6UltraLite, i.MX 7Dual Table continues on the next page.It contains a custom kernel-level API to manipulate logical channels. A logical channel represents a complete IPU processing flow. The IPU driver includes a frame buffer driver, a V4L2 device driver, and low-level IPU drivers.chloroacetic-acid.com/upload/files/20220531_070116.pdf Image Processing Unit (IPU) Drivers i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo, i.MX 6UltraLite, i.MX 7Dual HDMI This driver provides the support HDMI module HDMI Driver All V4L2 Output The Video for Linux 2 (V4L2) output driver uses the IPU post-processing functions for video output. The driver implements the standard V4L2 API for output devices. Video for Linux Two (V4L2) Driver All V4L2 Capture The Video for Linux 2 (V4L2) capture device includes two interfaces: the capture interface and the overlay interface. The capture interface records the video stream. The overlay interface displays the preview video. Video for Linux Two (V4L2) Driver All VPU The Video Processing Unit (VPU) is a multistandard video decoder and encoder that can perform decoding and encoding of various video formats. Video Processing Unit (VPU) Driver i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo Sound Drivers ALSA Sound The Advanced Linux Sound Architecture (ALSA) is a sound driver that provides ALSA and OSS compatible applications with the means to perform audio playback and recording functions using the audio components provided by Freescale's PMIC chips. ALSA has a user- space component called ALSAlib that can extend the features of audio hardware by emulating the same in software (user space), such as resampling, software mixing, snooping, and so on. The ASoC Sound driver supports stereo CODEC playback and capture through SSI. It implements one playback device for Tx and one capture device for Rx. SPI NOR Flash Memory Technology Device (MTD) Driver All NAND MTD The NAND MTD driver interfaces with the integrated NAND controller. It can support various file systems, such as UBIFS, CRAMFS and JFFS2UBI and UBIFSCRAMFS and JFFS2.The FEC requires an external interface adaptor and transceiver function to complete the interface to the Ethernet media. It supports half or full-duplex operation on 10M\100M\1G-related Ethernet networks. Fast Ethernet Controller (FEC) Driver All Bus Drivers I 2 C The I2C bus driver is a low-level interface that is used to interface with the I2C bus. This driver is invoked by the I2C chip driver; it is not exposed to the user space. The standard Linux kernel contains a core I2C module that is used by the chip driver to access the bus driver to transfer data over the I2C bus. Inter-IC (I2C) Driver All CSPI The low-level Enhanced Configurable Serial Peripheral Interface (ECSPI) driver interfaces a custom, kernel- space API to both ECSPI modules. A kernel configuration parameter gives the user the ability to choose the UART driver and also to choose whether the UART should be used as the system console. CHIPIDEA USB Driver All Table continues on the next page.It provides the interfaces to send and receive CAN messages. The CAN protocol was primarily designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN Driver i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo, i.MX 6UltraLite ASRC The Asynchronous Sample Rate Converter (ASRC) driver provides the interfaces to access the asynchronous sample rate converter module. Asynchronous Sample Rate Converter (ASRC) Driver i.MX 6Quad, i.MX 6Dual, i.MX 6DualLite, i.MX 6Solo WatchDog The Watchdog Timer module protects against system failures by providing an escape from unexpected hang or infinite loop situations or programming errors. The thermal driver will monitor the SoC's temperature in a certain frequency. It defines three trip points: critical, hot, and active. Thermal Driver All OProfile OProfile is a system-wide profiler for Linux systems, capable of profiling all running code at low overhead.The following sections describe the basic hardware and software operation and the software interfaces for MSL modules. First, the common modules, such as Interrupts and Timer are discussed. Because of the complexity of the SDMA module, its design is explained in SDMA relevant chapter. Each of the following sections contains an overview of the hardware operation. For more information, see the corresponding device documentation. 3.2 Interrupts (Operation) This section describes the hardware and software operation of interrupts on the device. 3.2.1 Interrupt Hardware Operation The Interrupt Controller controls and prioritizes a maximum of 128 internal and external interrupt sources. When an interrupt source is enabled and the corresponding interrupt source is asserted, the Interrupt Controller asserts a normal or a fast interrupt request depending on the associated Interrupt Type Register setting. Interrupt Controller registers can only be accessed in supervisor mode. The Interrupt Controller interrupt requests are prioritized in the following order: fast interrupts and normal interrupts in order of highest priority level, then highest source number with the same priority. There are sixteen normal interrupt levels for all interrupt sources, with level zero being the lowest priority. The interrupt levels are configurable through eight normal interrupt priority level registers. Those registers, along with the Normal Interrupt Mask Register, support software-controlled priority levels for normal interrupts and priority masking.The exception vector addresses can be configured to start at low address (0x0) or high address (0xFFFF0000). The Linux OS implementation running on ARM architecture chooses the high-vector address model.This function initializes the Interrupt Controller hardware and registers functions for interrupt enable and disable from each interrupt source. In addition to the native interrupt lines supported from the Interrupt Controller, the number of interrupts is also expanded to support GPIO interrupt and (on some platforms) EDIO interrupts. The following sections explain the hardware and software operation for the interrupts. 3.3.1 Interrupt Hardware Operation 3780,MX28 The Interrupt Collector module controls and prioritizes a maximum of 128 internal and external interrupt sources. Each source can be enabled and disabled by configuring the ENABLE bit in the dedicated Hardware Interrupt Collector Interrupt register. When an interrupt source is enabled and the corresponding interrupt source is asserted, the Interrupt Collector asserts a normal or a fast interrupt request to the ARM core depending on the ENFIQ bit value in the dedicated Hardware Interrupt Collector Interrupt register.There are four normal interrupt levels, with zero level being the lowest priority. The interrupt levels are configurable through the PRIORITY bits of the Hardware Interrupt collector Interrupt register. Only in supervisor mode can the Interrupt Collector registers be accessed. A number of IRQ sources can be expanded by using GPIO lines to assert interrupts. 3.3.2 Interrupt Software Operation 3780, MX28 In ARM based processors, normal interrupt and fast interrupt are two different exceptions. The exception vector addresses can be configured to start at a low address (0x0) or at a high address (0xFFFF0000). The ARM Linux implementation chooses the high vector address model.The timer hardware consists of four 32-bit 32 KHz timers. 3.4.1 Timer Hardware Operation The General Purpose Timer (GPT) has a 32 bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or falling edge. It has a 12-bit prescaler providing a programmable clock frequency derived from multiple clock sources. 3.4.2 Timer Hardware Operation 3780, MX28 Each of the four timers consists of a 1632-bit fixed count value and a 1632-bit free- running count value. The output of each timer's source select has a polarity control that allows the timer to operate on either edge. The timers have multiple clock sources that include the PWM output signals, the rotary encoder inputs and the on-chip 32 KHz XTAL that, in turn, can be programmed to 32 KHz, 8 KHz, 4 KHz or 1 KHz timer update cycles. Each of the four times have compare match register. When free-running counter equal match value, it issue a interrupt.The timer then registers its interrupt service routine and starts timing. The interrupt service routine is required to service the OS for the purposes mentioned in Timer. Both structures provide routines required for reading current timer values and scheduling the next timer event.The module implements a timer interrupt routine that services the Linux OS with timer events for the purposes mentioned in the beginning of this chapter. 3.4.8 Timer Programming Interface The timer module utilizes four hardware timers, to implement clock source and clock event objects. Both structures provide routines required for reading current timer values and scheduling the next timer event. The module implements a timer interrupt routine that services the Linux OS with timer events for the purposes mentioned in the beginning of this chapter. 3.4.9 Timer Unit Test The timer's operation can be verified through the proper operation of the Linux kernel itself. The timer must be programmed correctly before the Linux kernel boots. 3.5 Memory Map A predefined virtual-to-physical memory map table is required for the device drivers to access to the device registers since the Linux kernel is running under the virtual address space with the Memory Management Unit (MMU) enabled. 3.5.1 Memory Map Hardware Operation The MMU, as part of the ARM core, provides the virtual to physical address mapping defined by the page table. For more information, see the ARM Technical Reference Manual (TRM) from ARM Limited.The IOMUX module controls a pin usage so that the same pin can be configured for different purposes and can be used by different modules. This is a common way to reduce the pin count while meeting the requirements from various customers. Platforms that do not have the IOMUX hardware module can do pin muxing through the GPIO module. The IOMUX module provides the multiplexing control so that each pin may be configured either as a functional pin or as a GPIO pin. A functional pin can be subdivided into either a primary function or alternate functions. The pin operation is controlled by a specific hardware module. A GPIO pin, is controlled by the user through software with further configuration through the GPIO module. Otherwise, the IOMUX module needs to be configured to serve a particular purpose that is dictated by the system (board) design. If the pin is connected to an external UART transceiver and therefore to be used as the UART data transmit signal, it should be configured as the primary function. If the pin is connected to an external Ethernet controller for interrupting the ARM core, then it should be configured as GPIO input pin with interrupt enabled. Again, be aware that the software does not have control over what function a pin should have. The software only configures pin usage according to the system design. 3.6.1 IOMUX Hardware Operation The following discussion applies only to those processors that have an IOMUX hardware module. The IOMUX controller registers are briefly described in this section. For detailed information, see the pin multiplexing section of the IC Reference Manual.If it is configured as a GPIO pin, the pin is controlled by the user through software with further configuration through the GPIO module. If the hardware modes are chosen at the system integration level, this pin is dedicated only to that purpose which cannot be changed by software.