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digital computer logic lab manualJune 2013 Publisher: Dept.The main GUI interface of EWB Using Electronics Workbench for Design You may use EWB to: 1- Explore ideas and test preliminary circuits. 2- Refine circuits to full layout ( If circuit requires parts of a previous design) 3- Export files in format used by PCB (Printed Circuit Board) layout packages as move from design to production. Connecting Wires To attach an instrument to a circuit, point to a terminal on its icon so it highlights and drag a wire to a component.After that make the following changes - Connect the output of the converter to the red probe - Connect the Vcc line to the input of the inverter - Start simulating the circuit State your observation down: Observation: - In the same circuit above, stop the simulation and connect the ground to the input of the inverter. State your observation down: Task 6: Simple circuit; a clock source wi th a red probe Draw the following circuit and simulate it. Write down your observations. Notice that the clock (from Sources toolbox) frequency is 2 Hz. Note: You can change the default values of the clock by doing mouse right clicking on the clock and click on the “Component Properties.” as shown below: Write down your observations. Notice that the clock frequency is 2 Hz. Task 8: EWB Menu Name the following icons and state down their functions AND and NAND gates This gate gives high output (1) if all the inputs are 1’s.The truth table for the circuit appears in the logic converter's display. The two inputs of the gate are attached the A and B inputs of the logic converter. The circuit output C is connected to Out line of the logic converter. After clicking on the Truth Table button of the logic converter, the logic converter tries all possible combinations of the circuit input and derives its truth table. Task 6: Finding the truth table of a gate using the logic converter Repeat what you did in task 5 for the NOR gate. Show your connections in the circuit below.http://www.ricambiperauto.biz/img/brookstone-jumbo-universal-remote-manual.xml
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Show your connections in the circuit below. Note: you can obtain a three-input AND gate by drawing a regular two-input AND gate and then changing its Number of Inputs property as shown next. To learn how to directly convert a Boolean expression to circuit. ? To learn how to analyze a given digital logic circuit by finding the Boolean expression that represents the circuit. To learn how to analyze a given digital logic circuit by finding the truth table that represents the circuit. C’ The above function is implemented in the following digital logic Circuit Now after drawing the circuit above using EWB we find that its truth table is as shown below ( notice that logic 1 means connect the input to the Vcc line, and logic 0 means connecting the input to the ground) A B C Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 Task 2: Circuit analysis Find the Boolean expression that repr esents the outputs x and y shown in the following circuit. Find out the truth table of the circuit. Finally, click on the follo wing but ton that will generate the simplified form of the equation. To draw the circuit after simplification, you need to click on the fol lowing button, this will realize the simplified expression u sing basic gates. Background The NAND gate represents the complement of the AND operation. Its name is an abbreviation of NOT AND. The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the output, denoting that a complement operation is performed on the output of the AND gate. The NOR gate represents the complement of the OR operation. Its name is an abbreviation of NOT OR. The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output, denoting that a complement operation is performed on the output of the OR gate. A universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates.http://www.fototapetki.pl/upload/images/brookstone-jimi-rocker-clock-manual.xml In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all IC digital logic families. In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the other way around!! Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the other way around!! Implement any gate with NAND gates only To build an inverter ( NOT gate) using a NAND gate: All NAND input pins connect to the input signal A gives an output A’. An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND gate with its output complemented by a NAND gate inverter). An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters). The following figure shows all cases presented above An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter) An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR gate with all its inputs complemented by NOR gate inverters) The following figure shows all cases presented above Equivalent Gates A NAND gate is equivalent to an inverted-input OR gate. An AND gate is equivalent to an inverted-input NOR gate. An OR gate is equivalent to an inverted-input NAND gate.Lab Tasks Task 1: Simplifying two-input Boolean f unctions Simplify the following Boolean expres sion using a k-map of size 2x2. A B F (A, B) (original) Y (Simplified) Find out the truth table of the circuit.Use the Logic Converter of EWB to generate the truth table of the simplified circuit. A B C F (simplified) 0 0 0 0 0 1 Use the Logic Converter of EWB to generate the truth table of the simplified circuit.To learn how to build a parallel adder, subtracter, incrementer and decrementer using full adders.https://formations.fondationmironroyer.com/en/node/8272 Background The XOR gate (sometimes EOR gate, or EXOR gate) is a digital logic gate that implements an exclusive or; that is, a true output (1) results if one, and only one, of the inputs to the gate is true (1). If both inputs are false (0) or both are true (1), a false output (0) results. Next is the circuit representation of the XOR gate and its truth table. A B F1 0 0 0 0 1 1 1 0 1 1 1 0 Next is one way to build an XOR gate using NAND gates only The XOR logic gate can be used as a one-bit adder (or a Half-Adder; HA)that adds any two bits together to output one bit (the sum) and another bit that represents the carry out. As shown below The XOR logic gate can be used as a one-bit full adder that adds any three bits together to output one bit (the sum) and another bit that represents the carry out. As shown below Each one of the above circuits can be replaced with one single logic gate that gives the same truth table, that’s the Exclusive OR Gate or XOR. A B F No. of 1's 0 0 0 Even 0 1 1 Odd 1 0 1 Odd 1 1 0 Even Task 2: XNOR Gate Draw using EWB the following circuit the n fill its truth table: A B F 0 0 0 1 1 0 1 1 The above circuit can be replaced with one single logic gate that gives the same truth table, that’s the Exclusive NOR Gate or XNOR. Check t he circuit using a Logic converter. A B C A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Task 4: Half adder circuit The following diagram represents the Half Adder ( HA is a Logic Circuit that perfor ms 1- bit binary addition).P Q S C 0 0 0 1 1 0 1 1 Task 6: Implementing FA circuit using EWB Draw using EWB a full adder circuit; find out it s truth table and Boolean functions. Cin P Q Sum Cout 0 0 0 0 0 1 0 1 0 To learn how to build combinational logic circuits using multiplexers. Background In a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs.http://allquicker.com/images/breakup-manual.pdf Some examples of a combinational circuit include Multiplexers, De -multiplexers, Encoders, Decoders, Full and Half Adders etc. A Multiplexer is a combination of logic gates resulting into circuits with two or more inputs (data inputs) and one output. 4 Channel Multiplexer using Logic Gates The following circui t shows a 4x1 mux. Based on the binary value placed at the inputs “a” and “b”, what will appear at the circuit output Q is one of the following values: A, B, C, or D. The circuit above is implemented based on the following truth table. To learn how to build combinational logic circuits using decoders. Background In a Combinational Logic Circuit, the output is dependant at all times on the combination of its inputs. Some examples of a combinational circuit include Multiplexers, De -multiplexers, Encoders, Decoders, Full and Half Adders etc. A Decoder is a circuit with two or more inputs and one or more outputs. Its basic function is to accept a binary word (code) as an input and create a different binary word as an output.From the list, select either 74138 (3-8 decoder) or 74154 (4-16 decoder) as shown next. 74138 (3-8 decoder) A B C F 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 1 4 1 0 0 1 5 1 0 1 0 6 1 1 0 0 7 1 1 1 0 The above function can be implemented as shown next. Redraw this circuit using EWB. Task 2: Implementing multiple 3-variab le Boolean expressions using 3-8 deco der Implement the following three functions using 3-8 decoders.Background The truth table of the circuit is mapped into a 2x2 k-map. For three-input logic circuits. The truth table of the circuit is mapped into 4x2 or 2x4 k-maps. For four-input logic circuits. The truth table of the circuit is mapped into a 4x4 k-map. The ones (or zeros are grouped in twos, fours, or eights to do the simplification. Notice that the binary numbers in the horizontal and vertical edges of the k-map are gray codes.http://gsoam.ge/wp-content/plugins/formcraft/file-upload/server/content/files/16285a4b4a4418---c-22-5-manual-de-ordem-unida.pdf K-maps of 2x2, 2x4, 4x2 and 4x4 sizes Mapping the truth table into a k-map of size 2x2 Example (two-input circuites): Simplify the logic diagram below. Solution: (Figure below). Write the Boolean expression for the original logic diagram as shown below. Transfer the product terms to the Karnaugh map. Form groups of cells. Write Boolean expression for groups. Draw simplified logic diagram Gray code by bit width 2-bit 4-bit 00 01 11 10 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 3-bit 000 001 011 010 110 111 101 100 Mapping the four product terms above yields a group of four covered by Boolean A' Example (three-input circuits): Mapping the four p-terms yields a group of four, which is covered by one variable C. Example (three-input circuits): Covering these two with a group of four gives a simpler result.Visualize the group of four by rolling up the ends of the map to form a cylinder, then the cells are adjacent. We normally mark the group of four as above left. Out of the variables A, B, C, there is a common variable: C'. C' is a 0 over all four cells. Final result is C'. Example (three-input circuits): Example (four-input circuits): The above Boolean expression has seven product terms. They are mapped top to bottom and left to right on the K-map above. The other product terms are placed in a similar manner. Encircling the largest groups possible, two groups of four are shown above. The dashed horizontal group corresponds the the simplified product term AB. The vertical group corresponds to Boolean CD. Example (four-input circuits): Fold up the corners of the map below like it is a napkin to make the four cells physically adjacent. The other variables (A, B) are 0 in some cases, 1 in other cases with respect to the four corner cells. Thus, these variables (A, B) are not involved with this group of four. Therefore, the one group of eight is covered by one p-term: B'.denchumgiare.com/upload/files/canon-zr65mc-minidv-digital-camcorder-manual.pdf The difference is that while four Boolean variable product terms cover one cell, the three Boolean p-terms cover a pair of cells each. The three Boolean variable terms (three each) map as cell pairs, which is shown above. Note that we are mapping p- terms into the K-map, not pulling them out at this point. For the simplification, we form two groups of eight. Cells in the corners are shared with both groups. This is fine. In fact, this leads to a better solution than forming a group of eight and a group of four without sharing any cells. Above, three of the cells form into a groups of two cells. Such is the case illustrated below. Both are equally valid minimal cost solutions. The difference in the final solution is due to how the cells are grouped as shown above. A minimal cost solution is a valid logic design with the minimum number of gates with the minimum number of inputs. Example (four-input circuits): Below we map the unsimplified Boolean equation as usual and form a group of four as a first simplification step. It may not be obvious how to pick up the remaining cells. Pick up three more cells in a group of four, center above. There are still two cells remaining.On a cautionary note, do not attempt to form groups of three. Groupings must be powers of 2, that is, 1, 2, 4, 8. Start by forming a couple of groups of four after mapping the cells. The two solutions depend on whether the single remaining cell is grouped with the first or the second group of four as a group of two cells. That cell either comes out as either ABC' or ABD, your choice. Either way, this cell is covered by either Boolean product term. Final results are shown above. The biggest picture of all- Simplifying using K -maps, Boolean algebra. Example (four-input circuits): Below we have an example of a simplification using the Karnaugh map at left or Boolean algebra at right. Then, plot the single ABCD cell.Produce a Product- Of -Sums solution. Compare the POS solution to the previous SOP.http://www.hotelamoha.it/wp-content/plugins/formcraft/file-upload/server/content/files/16285a4c5b9425---C-152-operating-manual.pdf ResearchGate has not been able to resolve any references for this publication. Advertisement Recommendations Discover more Project The X-Pro Project Sulieman Bani-Ahmad Aims: Designing and implementing syllabus-oriented question-bank system that is capable of producing paper-based exams with multiple forms along with answer keys. The study is motivated by the fact that student number in schools and universities is continuously growing at high, non-linear, and uncontrolled rates. This growth, however, is not accompanied by an equivalent growth of educational resources (mainly: instructors, classrooms, and labs). A direct result of this situation is having relatively large number of students in each classroom. It is observed that providing and using online-examining systems could be intractable and expensive. As an alternative, paper-based exams can be used. One main issue is that manually produced paper-based exams are of low quality because of some human factors such as instability and relatively narrow range of topics. Further, it is observed that instructors usually need to spend a lot of time and energy in composing paper-based exams with multiple forms. Therefore, the use of computers for automatic production of paper-based exams from question banks is becoming more and more important. Methodology: The design and evaluation of X-Pro Milestone are done by considering a basic set of design principles that are based on a list of identified Functional and Non-Functional Requirements. Deriving those requirements is made possible by developing X-Pro Milestone using the Iterative and Incremental model from software engineering domain. Results: We demonstrate that X-Pro Milestone has a number of excellent characteristics compared to the exam-preparation and question banks tools available in market.https://www.lipfish.no/wp-content/plugins/formcraft/file-upload/server/content/files/16285a4c7609c4---c-24-digidesign-manual.pdf Some of these characteristics are: ease of use and operation, user-friendly interface and good usability, high security and protection of the question bank-items, high stability, and reliability. Further, X-Pro Milestone makes initiating, maintaining and archiving Question-Banks and produced exams possible. Putting X-Pro Milestone into real use has showed that X-Pro Milestone is easy to be learned and effectively used. We demonstrate that X-Pro Milestone is a cost-effective alternative to online examining systems with more and richer features and with low infrastructure requirements. Request-partitionin g-based strategies work by partitioning parallel requests at their longest dimension. While useful in many circumstances, the success of locating related publications via keyword-based sea rching paradigm is influenced by how users choose their keywords. Example-based searching, where user provides an example publication to locate similar publications, is also becoming commonplace in digital libraries. The software also allows them to produce exam instances out of these question banks. The produced exams are printable and are provided with proper answer key. Read more Article Full-text available AC 2012-3784: ANAEROBIC DIGESTOR OF ORGANIC WASTE PRO- CESSING: A BIOMASS ENERGY PRODUCTION PROJECT Wagdy Mahmoud K Pradeep Behera Wagdy H. Mahmoud is an Associate Professor of electrical engineering at the Electrical Engineering Department at UDC. Esther Ososanya is a professor of electrical and computer engineering at the University of the District of Columbia. During her career, Ososanya has worked for private industry as a circuit development engineer and as a software engineer, in addition to her academic activities. She received her education in the United Kingdom, where she received her Ph.D. in electrical engineering from the University of Bradford in 1985.www.demirdokumservisiankara.com/image/files/canon-zr65mc-manual.pdf She was also a Visiting Professor at Michigan Technological University for five years, and an Associate Professor at Tennessee Technological University for seven years prior to joining the University of the District of Columbia in the Fall of 2001. Ososanya is interested in new applications for VLSI, MEMS, parallel processing, and pipeline architecture. In recent years, she has worked with colleagues to apply these technologies to such environmental problems as watershed monitoring, biosensors, and sustainable energy applications. View full-text Article Hardware Design Verification: Simulation and Formal Method-Based Approaches January 2005 William K. Lam The Practical, Start-to-Finish Guide to Modern Digital Design Verification As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. College students will find that coverage of verification principles and common industry practices will help them prepare for jobs as future verification engineers. Author William K. Lam, one of the world's leading experts in design verification, is a recent winner of the Chairman's Award for Innovation, Sun Microsystems' most prestigious technical achievement award. Drawing on his wide-ranging experience, he introduces the foundational principles of verification, presents traditional techniques that have survived the test of time, and introduces emerging techniques for today's most challenging designs. Throughout, Lam emphasizes practical examples rather than mathematical proofs; wherever advanced math is essential, he explains it clearly and accessibly. Read more Article Synchronous FSM Design Methodology for Low Power Smart Sensors and RFID Devices Matej Machalec Jakub Stastny This contribution focuses on integration of low power design approaches for synchronous Finite State Machi-nes (FSMs) designs into a standard RTL digital design flow. Text summarizes current techniques and presents a methodo-logy for design of FSMs with reduced power consumption targeted to low-power smart sensors and RFID devices. Described methodology allows to reduce device power consumption and is compatible with all design tools. The methodology is also independent on the designed device and fully reusable between projects. The addition of low-power customized FSM encoding needs only one additional design step requiring only small amount of coding; the effort overhead is nearly zero. The contribution to the digital logic design is evaluated by integration of the methodology into our ASIC design flow during design of a real ASIC smart sensor platform; a reduction of power consumption of up to 70 in the FSMs is demonstrated while the power optimization pro-cess itself took less than one manday. Read more Download citation What type of file do you want. RIS BibTeX Plain Text What do you want to download. Citation only Citation and abstract Download ResearchGate iOS App Get it from the App Store now. Install Keep up with your stats and more Access scientific knowledge from anywhere or Discover by subject area Recruit researchers Join for free Login Email Tip: Most researchers use their institutional email address as their ResearchGate login Password Forgot password. Keep me logged in Log in or Continue with LinkedIn Continue with Google Welcome back. Keep me logged in Log in or Continue with LinkedIn Continue with Google No account. All rights reserved. Terms Privacy Copyright Imprint. Boole's method of logical inference allows conclusions to be drawn from any proposition involving any number of terms. Boolean logic demonstrates that the conclusions found are logically contained in the original premises (Encyclopedia Britannica, 2003).These values are combined in equations to yield results that also have these two values. The equations are represented by truth tables that show the inputs to the equation and the outputs produced for those inputs. The rows of the table contain all the possible combinations of 1s and 0s for the inputs. The number of rows is determined by the number of possible combinations.Think of an ATM that has three options: print a statement, withdraw money, or deposit money. The ATM will charge a fee to (1) withdraw money or (2) print a statement without depositing money. The intent of the problem is to develop a Boolean equation and logic circuit that will determine after which possible combination of actions will someone get charged a fee. First, a truth table should be made for all the possible combinations of inputs. The inputs are the ATM's three functions. Let variable stand for printing a statement, for withdrawing money, and for depositing money. There is one output, which is whether or not the ATM will charge a fee. The output will be denoted by. The truth table in Table 1 shows all the possible combinations of the inputs and their corresponding outputs.There are symbols for each of these gates, and the connections between them are represented by lines running from the output of one gate to the input of another. A line can connect only one output to each input. There are seven of these gates: the NOT, AND, OR, NAND, NOR, XOR, and XNOR gates. Only the first three will be used in this lab (Figure 1).It is an inverter. It has one input and produces its opposite as the output. For example, if a 1 value is put into a NOT gate, a 0 value is outputted, as seen in Table 2. The symbol for the operation is a horizontal bar over the variable. The truth table for a NOT gate is shown in Table 2.If all the inputs are true, the output is also true. But if either of the inputs is false, the output is also false. An AND gate can have two or more inputs, but for this lab, it will have two inputs (denoted by A and B in Table 3). The truth table for an AND gate is shown in Table 3.If either of the inputs is true, the output is also true. But if all the inputs are false, the output is also false. An OR gate can have two or more inputs, but for this lab, it will have two inputs (denoted by A and B in Table 4). The truth table for an OR gate is shown in Table 4.All the combinations that yield an output of 1 are kept, and the equation is written. This is called a Sum of Products solution. Only the combinations that yield an output of 1 are kept because the Boolean equation intends to represent a quantitative function for when the result will have a value of true (when a fee is charged in the example of the ATM machine). The combinations that yield an output of 0 are essentially discarded because there is no interest in when the result has a false value. The Boolean equation for the ATM example can be seen in Figure 2.If an input is true, the variable can be used as is; for an input that is false, the variable is inverted using the horizontal bar (the NOT operation). Since the output is true if any of the combinations are true, the equation is formed by using addition operations (the OR operation) on all the terms formed by the product of each combination.However, this equation can be simplified using a Karnaugh map (K-map). A K-map identifies and eliminates all the conditions that do not contribute to the solution. The resulting simplified Boolean equation is used to build the digital circuit and will be a combination of the logic gates described above.For an equation with three inputs, usually all the combinations of the first two inputs are shown as four columns and the values for the third input are shown as two rows. For four inputs, all the combinations of the third and fourth inputs are shown as four rows. Only one value can change at a time in adjacent rows or columns. For example, in Table 5, the columns change from 00 to 01 to 11 to 10. Table 5 illustrates the K-map for the ATM example.Look for cells that can physically be boxed together, where the number of cells in the box is a power of 2 (1, 2, 4, or 8 and so on). The boxes are allowed to overlap so the same cells can be used more than once. Look for the biggest boxes first, and keep finding smaller boxes until all the cells with a 1 in them are used. This means that sometimes just single cells will remain at the end. The cells in the K-map for the ATM example can be grouped like what is shown in Figure 3.This means is that if the conditions for either box are true, the output will be true. This also means that the simplified Boolean equation will only have two terms. The term for each box can be determined by observing which variables are constant throughout each cell of that box. For the red box, only remains constant through the four cells.For the blue box, and remains constant through the two cells, while switches from the left cell to the right cell. The two boxes yield the simplified Boolean equation shown in Figure 4.First, a NOT operation is performed on by inputting and outputting through a NOT gate. Then, the and inverted are inputted into an AND gate, as denoted by them being multiplied in Figure 4. Finally, the result of the AND operation between the and inverted and the are inputted into an OR gate, as denoted by the addition function in Figure 4. The final combinational logic circuit can be seen in Figure 5.In addition to milk and butter, Farmer Georgi sells fresh eggs at the Union Square Greenmarket in Manhattan. It is imperative that Farmer Georgi protects the hen that produces eggs for his business.A fox has been attempting to eat the hen by hiding in a barn. The hen can move freely from one barn to the other. Farmer Georgi sometimes stores corn in one barn and sometimes in the other, but he never stores it in both at the same time. The hen would like to eat the corn and the fox would like to eat the hen. Farmer Georgi needs an alarm system that uses digital logic circuits to protect the hen and the corn. The design should use the fewest logic gates and input variables possible. The alarm will sound if:If the procedure is completed without verifying that the ICs work, problems may occur in the circuit that require additional time and troubleshooting.The code compares those results to the expected result. The goal is to determine if the gates are outputting the correct results. After, remove the chips carefully from the Arduino board. Use 1 for Barn 1 and 0 for Barn 2 (1 does not mean true and 0 does not mean false for the inputs). For the alarm output, use 0 to indicate that the alarm should be off, and 1 to indicate that the alarm should be on. Assign the input variables. Include all possible scenarios for the hen, the corn, and the fox. To do this, analyze the three inputs and logically determine if the alarm will sound in each scenario. Place a 1 in the output column if the alarm will sound and a 0 if it will not. Create a Boolean equation from this table that includes each of the inputs that produced a true output. Use the Boolean equation to fill in the 1s and 0s on the K-map. The 1s may only be boxed in powers of 2 starting with the largest possible combination and working down to the smallest. The outcomes that do not contribute to the solution are to be discarded. Write this simplified Boolean equation down. Open LabVIEW and select New VI.Place a Boolean indicator on the front panel to represent the output. On the board, identify each of the three IC chips as an AND, OR, or NOT gate. To do this, read the number on the chip and match it with the numbers shown in Figure 7. Look for the notch at one end of each chip to orient the chip to the diagrams in Figure 7 and to match the pins.Insert the other end of the lead into Pin 14 of the IC chip. Repeat this process for all three chips.