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Any delivered purchase shall be returned or surrendered upon demand by the Auctioneers prior to the return of payment. Flammable, noxious, corrosive and pressurized substances may be present. Heavy equipment is being operated and electrical circuits may be live. Every person at the auction site, before, during and after the auction sale shall be deemed to be there at their own risk with notice of the condition of premises, the activities on the premises and the conduct of third parties.http://bizwd.com/wp-content/plugins/formcraft/file-upload/server/content/files/162844ac65647e---bullard-edp10-manual.pdf No person shall have any claim against the Auctioneers, their agents, employees or principals for any injuries sustained, nor for damages to, or loss of property which may occur from any cause whatsoever. Auctioneers, at any time, and at their sole discretion, without notice or liability to buyer may: (a) withdraw or cancel the sale of any Lot, or (b) offer any Lots in groups or with privilege No person shall bid on any Lot: (a) of which he is the consignor; or (b) as agent, associate, or on behalf of the consignor. This store was just recently closed and all items in this store are still intact. Disconnects and removals must be performed by qualified personnel only. Registering for this event means you agree to both the Live Auction World website terms and conditions and also Woody’s Auctions Ltd.Getting notified via SMS Text Message will require you to verify your cell phone via the profile page in your account. Login to post Please check the base of your notebook for sticker label. (15 characters) The serial number is listed directly below the barcode. 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Alte ra assumes no responsibility or liability ar ising out of the application or use of any i nformation, product, or service described herein except as expr essly agreed to in writing by Altera. Alter a cust omers are advis ed to obta in the latest v ersion of device s pecificat ions before relying on any published information and before plac ing orders for prod ucts or serv ices. September 2015 Altera Corporation Str atix V GX FPGA Development Board Reference Manual ISO 9001:2008 Registered.argentinapools.com/contents//files/car-manual-honda-jazz.pdf General Description The Stratix V GX FPGA development boar d pr ovides a hardwar e platform fo r developing and prototyping high-performance and high-bandwid th application designs. The boar d pr ovides a wide range of peripherals and me mory interfaces to facilitate the development of Stratix V GX FPGA designs. T wo High-Speed Mezzanine Card (HSMC) co nnectors ar e available to add additional functionality via a variety of HSMC cards available from both Altera and various partners.Design advancements and innovations, such as the PCI Expr ess har d IP implementation, partial reconfiguration, and programmable power technology ensur e that designs implemented in the Stratix V GX FPGAs operate faster, with lower power than in previous FPGA families.Configuration, Status, and Setup Elements J10 JT AG he ader Provides access to the JT AG chain by using an extern al USB-Blaster cable (disables the on -board USB-Blaster II). J7 On-Board USB-Blaster II Micro-USB 2.0 conne ctor for programming and debugging the FPGA. SW3 JT AG DIP switch Enables and disables devices in the JT AG chain. This switch is located on the back of the board. SW5 Board settings DIP switch Controls the MAX V CPLD System Controller functions such as clock select, clock enable, factory or user des ign load from flash and FACTORY signal command sent at power up. This switch is located at the bottom of the board. This switch is locate d at the back of the boa rd. S3 Program select push button T oggles the program LEDs which selects the program image that loads from flash memory to the FPGA. S2 Program load push button Configures the FPGA from flash memor y image based on the prog ram LEDs. D4, D5, D6 Program LEDs Illuminates to show the LED sequence that determines which flash memory image loads to the F PGA when you press the program load push button. D17 Configuration done LED Illuminates when the FPGA is configured. D15 Load LED Illuminates during FPGA configuration. D16 Error LED Illuminates when the FPGA configuration from flash fails. D24 Power LED Illuminates when 5-V power is present. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle. The LEDs are either off when not in use or on when in us e but idle. D29, D30, D31, D32 Ethernet LEDs Indicate the connection speed as well as transmit or receive activity. D3, D13 HSMC port A LEDs Y ou can configure these LEDs to indicate transmit or receive activity. D1 HSMC port A Present LED Illuminates when a daughtercard is plugged into the HSMC port A. D11, D14 HSMC port B LEDs Y ou can configure these LEDs to indicate transmit or receive activity. D35, D36, D37 PCI Express Link LEDs Y ou can configure these LEDs to display the PCI Express link width (x1, x4, x8). U38 Quad-output oscillator Programmable oscillator with default frequencies of 100 MHz, 156.25 MHz, 625 MHz, and 2 70 MHz. U46 Quad-output oscillator Programmable oscillator with default frequencies of 125 MHz, 644.53125 MHz, 282.5 MHz, a nd 125 MHz. X6 148.5 M oscillator 148.500-MHz voltage controlled cr ystal oscillator for SDI video. This oscillator is programmable to any frequency between 20-810 MHz. J13, J14 Clock input SMAs Drives L VPECL-co mpatible clock inputs into the clock multiplexer buffer. U4 100 M oscillator 100-MHz cr ystal oscillator for the MAX V CPLD System Con troller. General User Input and Output D7-D10, D18-D21 User LEDs Eight bi-color LEDs (green and red) for 16 user LEDs. Illuminates when driven low. SW1 User DIP switch Octal user DIP switches. When the switch is ON, a log ic 0 is selected. S1 MAX V reset push button The default reset for the MAX V CPLD System Controller. S4 CPU reset push button Th e default reset for the FPGA logic. S5, S6, S7 General user push button Three user push buttons. Driven low when pressed. Memory Devices U12, U17, U21, U23, U28 DDR3 x72 A 1152-MB DDR3 SDRAM with a 72-bit data bus. The 72-bit data bus consists of four x16 devices and one x 8 device with a single address or command bus. The device has a separate 18-bit read and 18-bit write port with DDR signalling at up to 550 MHz. U20 RLDRAM II x18 A 72-MB CIO RLDRAM II with a 18-bit data bus. The 18-bit data bus consists of a single x18 device with a single address or comma nd bus. U10, U11 Flash x32 T wo 512-Mb synch ronous flash devices with a 16-bit data buses for non-volatile memor y. The board supports two flash devices of 16-bit inter face each, which combine to allow for 1-Gbyte (GB) synchronous flash with a 32-bit data bus. Communication Ports J18 PCI Express edge connector Made of gold-plated edge fingers for up to ?8 signaling in either Gen1, Gen2, or Gen3 mode. J12 QSFP conne ctor Provides four transceiver channels for a 40G QSFP module. J1 HSMC port A Provides eight transceiver channels and 84 CMOS or 17 L VDS channels per the HSMC specification. Video and Display Ports J16, J17 SDI video port T wo 75-.J4 DC input jack Accepts a 19-V DC power supply.Configuration This section describes the FPGA, flash memory, and MAX V CPLD System Controller device programming methods that the Stratix V GX FPG A development board supports. FPGA Programming over On-Board USB-Blaster II The on-board USB-Blaster II is implemente d using a micr o-USB type-B connector (J7), a USB 2.0 PHY device, and an Alt era MAX II CPLD EPM570 GM100 (U14). This allows the configuration of the FPGA us ing a USB cable which connects di rectly betw een the USB port on the boar d (J7) and a USB port on a PC running the Quartus II softwar e. The on-board USB-Blaster II normally masters the JT AG chain.Push al l the switches in the ON position to only have the FPGA in the chain. System Console USB Interface The System Console USB interfac e is a fast parallel interface. T ogether with the soft logic supplied by Al tera, this interface provides a System Consol e master for debu g access.Flash Programming Flash programming is possible through a variety of methods using the Stratix V GX FPGA device. The first method is to use the factory desi gn called the Board Update Portal. This design is an embedded web server, which serves the Board Update Portal web page. The develo pment board implement s the Altera PFL megafunction for flash programmi ng. The PFL megafunctio n is a block of logic that is prog rammed into an Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for writing to a compatible fl ash device. This pr e-built design contains the PF L megafunction that a llows you t o write either page 0, page 1, or other ar eas of flash over the USB interface using the Quartus II software. Use this method to restor e the development board to its factory def ault settings. Other methods to program the flash can be used as well, in cluding the Nios II processor.FPGA Programming from Flash Memory On either power-up or by pr essing the program load pus h button (S2), the MAX V CPLD System Controller ’s para llel flash loader configures the FPGA from the flash memory. The system controller us es th e Altera Parallel Flash Load er (PFL) megafunction whic h read s 32-bit data from t h e flash memory and converts it to fast passive parallel (FPP) format. This 32-bit data is then written to the FPGA ’s dedicated configuration pins du ring configuration. There ar e three pages re served for the FPGA config uration data —factory har dware (page 0), user har dware 1 (page 1), and user hardwar e 2 (page 2).FPGA Programming over External USB-Blaster The JT AG programming header provides an other method for config uring the FP GA (U15) using an external USB- Blaster device with the Quartus II Pr ogrammer running on a PC. Status Elements The development boar d includes board-specific status LEDs and switches for enabling and configuring various featu res on the boar d, as well as a 16 character ? 2 line LCD for displaying board power and temperature measur ements. This section describes these status elements. Status LEDs S u r f a c e m o u n t L E D s i nd i c a t e t h e v a r i o u s s t a t u s o f t h e b o a r d. Illuminates when the MAX V CPLD System Controller is actively configuring the FPGA. Driven by the MAX V CPLD System Controller. Illuminates when the MAX V CPLD System Controller fails to configure the FPGA. Illuminates when the FPGA is succ essfully configured. Blinks to indicate Ethernet PHY transmit activity. Driven by the Mar vell 88E1111 PHY. Blinks to indicate Ethernet PHY receive activity. Illuminates to indicate Ethernet linked at 100 Mbps connection speed Driven by the Marvell 88E1111 PHY. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed. Drive n by the Mar vell 88E1111 PHY. Illuminates when the HSMC port A has a board or cable plugged-in such that pin 160 becomes grounded. Driven by the add-in card. Illuminates when the HSMC port B has a board or cable plugged-in such that pin 160 becomes grounded. Setup Elements The development boar d includes several differ ent kinds of setup elements. D12 TEMP OVERTEMPn Red LED. Illuminates when a heat sink or fan should be installed. Driven by the MAX1619 thermal sensor OVERTEMPn signal. Board-Specific LEDs Component References and Manufacturing Information Board Reference Description Manufacturer Manufacturer Part Number Manufacturer Website D1, D2, D4-D 6, D15, D17, D29-D32 Green LEDs Lumex Inc. SML-LX1206GC-TR www.lumex.com D16 Red LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com D24 Blue LED Lumex Inc. OFF: Programmable oscillator input clock select (default 100 MHz). OFF: On-Board oscillator disabled. ON. JT AG Control DIP Switch The JT AG control DIP switch (SW3) provides you an option to either remove or include devices in the active JT AG chain. However, the Stratix V GX FPGA device is always in the JT AG chain. OFF: Load factory design from flash at power up. OFF: Send F ACTORY command at power -up. OFF: MAX V CPLD System Controller in-chain. OFF: PCI Express edge connector is the chain master. This push button is the default logic reset for the CPLD logic. Th e pu s h b u t to n fo rc es a rec o nf igurat ion of the FPGA from flash memory. This push button is the default logic re set for the FPGA logic. The MAX V System Controller also drives this push button during POR. When you enable the signal in the Quartus II softwar e, and then pulled high on the board, this push button rese ts every r egister within the FPGA with a low signal.Can also support 2x L VTTL inputs. Can also support 2x L VTTL inputs. Can also support 2x CMOS outputs. Ca n also support 2x CMOS outputs. Can a lso support 2x CMOS outputs. Boar d referenc es S5, S6, and S7 are push buttons that allow yo u to interact with t he Stratix V GX FPGA device. When you pre ss and hold down t he pu sh button, the device pin is set to logic 0; when you r elease the push button, the device pin is set to logic 1. Ther e is no board-specific function for these ge neral user push buttons. ECS-35 25-1000-B-TR www. ecsxtal.com X3 50 MHz 1.8-V oscillator ECS, Inc. User -Defined DIP Switches Board r e ference SW1 is an 8-pin DIP switch. The switches are user -defined, and are for additional FPGA input control. Ther e is no board-specific function for these switches. When the switch is in the CLOSED or ON position, a logic 0 is selected. This section describes all user-defined LEDs. General User -Defined LEDs Board r e ferences D7 thr ough D10 and D18 through D21 ar e eight bi-color user LEDs which allow status and debugg ing signals to be driven to the LEDs from the designs loaded into the Stratix V GX FPGA device. These bi-color LEDs ar e in r ed and gre en, which combines to a total of 16 unique user LEDs. The LEDs il luminate when a logic 0 is driven, and turns off when a logic 1 is driv en. Ther e is no board-specific function for these LEDs.